An application for xe2x80x9cESD Protection Device for Open drain I/O Pad in Integrated Circuits with a Merged Layout Structurexe2x80x9d, (docket VIS88-031) assigned to the assignee of this invention, has a related disclosure.
This invention relates generally to circuits for semiconductor chips and more specifically to circuits with improved protection against electrostatic discharge (ESD) stress at an input-output pad of the chip.
ESD voltages are a familiar problem for developers of semiconductor chips for integrated circuit devices. An ESD voltage appears at an input-output pad of a chip when, for example, a voltage is picked up by a conductor that runs between the pad and a circuit node external to the chip. A pad is a small region on a chip were external conductors can be attached to the chip. A pad is usually connected to the input of an input buffer circuit or to the output of a driver circuit or to both.
One familiar driver circuit is an inverter formed by two NMOS FETs. An upper FET is connected to conduct between the output pad and Vdd and a lower FET is connected to conduct between the output pad and Vss. (Vss and Vdd are the usual designations for the power supply terminals of the chip.) The gates of the FETs receive binary signals that in one state turn off the lower FET and turn on the upper FET to pull the output pad up. In the other binary state, the signals at the gates of the FETs turn off the upper FET and turn on the lower FET and pull the output pad down.
ESD protection device limits the ESD voltage to a value that will not damage the internal circuits of the chip that are connected to the pad. An ESD protection device creates a low resistance current path that clamps the voltage at the pad to a safe value. Sometimes a resistor is connected in the signal path between the pad and the protection device to further isolate the pad voltage from other components.
An ESD current path can be established in response to a high ESD voltage when a semiconductor junction breaks down. This junction breakdown occurs because the voltage on the ESD side of the junction has reached a break down value with respect to the voltage on the other side of the junction. The voltage on the other side of the junction is commonly established by the power supply nodes, Vss and Vdd, and the ESD current path ordinarily It includes Vss or Vdd. The ESD current can also flow in a path between Vss and Vdd.
The driver circuit that has just been described can be used for ESD protection. When a high positive voltage appears at the pad with respect to Vss, the substrate-drain junction of the lower FET is reverse biased and it breaks down at a predetermined voltage. In a similar way, the upper FET provides protection against an ESD voltage that appears between the pad and Vdd. These circuits provide protection for an ESD voltage of either polarity.
Commonly, the drain diffusion is made larger to handle the ESD current. The larger drain increases the capacitance at the pad and in this way slows the rise and fall of logic pulses that appear at the pad in the normal operation of the chip.
Sometimes an open drain driver is used with an input-output pad. This driver circuit is like the circuit just described except that it does not have the upper FET: in normal operation the driver output is pulled down in the way described but it is pulled up by the external circuits that are connected to the pad. An open drain driver circuit does not in general provide a suitable path for an ESD current to Vdd.
The prior art has suggested many other devices for creating this path for ESD currents at the pad.
One object of our invention is to provide improved ESD protection for the internal circuits of a chip that are connected to a pad having an open drain driver circuit. A more specific object is to provide protection against an ESD voltage that appears between the pad and power supply terminal Vdd.
We provide a first field FET connected between the pad and Vdd. As is conventional, the field FET has a source diffusion, a drain diffusion, an intervening channel, and a field oxide over the channel. The field FET does not have a gate electrode. It turns on when a break down occurs at the reverse biased junction of the drain diffusion or the source diffusion.
We also provide, optionally, a second field FET that conducts an ESD current (of either polarity) between Vss and Vdd. When an ESD voltage appears between the pad and Vdd, the driver conducts between the pad and Vss and the second field FET conducts between Vss and Vdd.
The driver FET comprises two parallel FETs formed symmetrically about a common (shared) drain diffusion, as in the related application.
The first field FET is formed by the drain diffusion of the open drain driver and a frame that surrounds (or partly surrounds) the driver. The frame is of the same conductivity type as the drain and source diffusions of the driver, and it is connected to Vdd. The drain of the driver forms the diffusion for the pad end of the first field FET and the frame forms the diffusion for the Vdd end.
A second field FET is formed similarly by the frame and the source diffusion of the driver, and it conducts between the source diffusion at Vss and the frame at Vdd.
In one embodiment, the frame around the driver FET is rectangular or square and several driver FETs are formed in a row and column array and connected to conduct in parallel to provide a selected output current at the pad.
In one embodiment, the frame is a partial frame that borders the drain and source diffusions of the driver FET along opposite sides of the driver FET structure and thereby forms only the first field FET between the pad and Vdd.
Other features of the invention will appear in the description of my preferred embodiment.